Samsung has reportedly come up with a new way to solve for a bottleneck problem in AI chips, which is said to be a new type of 3D memory architecture that go from “flat integration to vertical integration.”
In other words, Samsung’s idea for the 3D memory architecture is stacking the components on top of each other as opposed to laying them all flat on the board. When you have no more room to build out, you build up, which is what Samsung’s new 3D memory architecture is doing based on the new announcement from Samsung.
New 3D memory architecture from Samsung will have 400-plus layers
Officially called the zHBM and zNAND-O concepts, Samsung’s new architecture will have things stacked as a means of advancing future AI infrastructure. This design will stack the HBM on top of the AI accelerators. Typically, these series of components are lined up next to each other, but that takes up more horizontal real estate. Therein lies another problem: the bottleneck.
With the old designs, or in this case the still-current designs in terms of what’s available to manufacturers to use in their products, memory bandwidth has become a new issue, with data having to travel further distances, back and forth between each other. This has slowed things down. Samsung’s new designs, by stacking the components, allows data to travel back and forth between the HBM and the AI accelerators at a faster rate.
Samsung says its new concept designs provide higher bandwidth and improved power efficiency. Specifically, Samsung states that “zHBM can achieve more than 10 times the memory density of HBM5 while enhancing energy efficiency threefold and reducing thermal resistance by more than half, maximizing the stability and power efficiency of high-capacity, high-bandwidth systems.”
Samsung is also introducing its new V10-BV-NAND, which it says has “400-plus layers” to help increase storage density.
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